1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which is constructed as one chip by a plurality of sub chips adjacent to each other on a wafer.
2. Description of the Related Art
The memory capacity of a memory device such as a dynamic random access memory (DRAM) has been increased while reducing the manufacturing yield. As a result, it has been suggested that a plurality of sub chips be combined to form one chip, to improve the manufacturing yield (see JP-A-HEI4-7867). This will be explained later in detail.
In the above-mentioned prior art semiconductor device, however, an alignment margin for assembling sub chips has to be provided in each of the sub chips, to reduce the integration. Also, in a large capacity semiconductor device such as a 256 Mbit DRAM device and a 1 Gbit DRAM device, a 4-sub-chip configuration, an 8-sub-chip configuration, . . . have to be used, and as a result, the number of function discrimination pads is increased, and also, the alignment margin for the assembly is also increased to reduce the integration.